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HY62V8200B Series
256Kx8bit CMOS SRAM
Document Title
256K x8 bit 3.3V Low Power CMOS slow SRAM
Revision History
Revision No 03 History Initial Revision History Insert Revised - Improved operating current Icc1 : 60mA -> 35mA Change the Notch Location of sTSOP - Left-Top => Left-Center Marking Information Add Revised - AC Test Condition Add : 5pF Test Load Changed Logo - HYUNDAI -> hynix - Marking Information Change Draft Date Jul.29.2000 Remark Final
04
Sep.04.2000
Final
05
Dec.04.2000
Final
06
Apr.30.2001
Final
This document is a general product description and is subject to change without notice. Hynix Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 06 / Apr. 2001 Hynix Semiconductor
Y62V8200B Series
DESCRIPTION
The HY62V8200B is a high speed, low power and 2M bit CMOS SRAM organized as 262,144 words by 8bit. The HY62V8200B uses high performance CMOS process technology and designed for high speed low power circuit technology. It is particularly well suited for used in high density low power system application. This device has a data retention mode that guarantees data to remain valid at a minimum power supply voltage of 2.0V.
FEATURES
Fully static operation and Tri-state output TTL compatible inputs and outputs Battery backup( LL-part ) -. 2.0V(min) data retention Standard pin configuration -. 32-sTSOPI-8X13.4, 32-TSOPI -8X20 (Standard and Reversed)
Product Voltage Speed Operation No. (V) (ns) Current/Icc(mA) HY62V8200B 3.0~3.6 70/85/100 5 HY62V8200B-E 3.0~3.6 70/85/100 5 HY62V8200B-I 3.0~3.6 70/85/100 5 Note 1. Blank : Commercial, E : Extended, I : Industrial 2. Current value is max.
Standby Current(uA) 25 25 25
Temperature (C) 0~70 -25~85(E) -40~85(I)
PIN CONNECTION
A11 A9 A8 A13 /WE CS2 A15 Vcc A17 A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 /OE A10 /CS1 DQ8 DQ7 DQ6 DQ5 DQ4 Vss DQ3 DQ2 DQ1 A0 A1 A2 A3 A11 A9 A8 A13 /WE CS2 A15 Vcc A17 A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 /OE A10 /CS1 DQ8 DQ7 DQ6 DQ5 DQ4 Vss DQ3 DQ2 DQ1 A0 A1 A2 A3
TSOP-I (Standard)
sTSOP-I (Standard)
PIN DESCRIPTION Pin Name /CS1 CS2 /WE /OE A0 ~ A17 I/O1 ~ I/O8 Vcc Vss Pin Function Chip Select 1 Chip Select 2 Write Enable Output Enable Address Input Data Input/Output Power(3.0V~3.6V) Ground
BLOCK DIAGRAM
A0 ROW DECODER SENSE AMP ADD INPUT BUFFER
I/O1
COLUMNDECODER
DATA I/O BUFFER
MEMORY ARRAY 256K x 8
WRITE DRIVER
A17
I/O8
/CS1 CS2 /WE /OE
CONTROL LOGIC
Rev 06 / Apr. 2001
2
Y62V8200B Series
ORDERING INFORMATION Part No. Speed Power Temp. HY62V8200BLLT1 70/85/100 LL-part HY62V8200BLLR1 70/85/100 LL-part HY62V8200BLLST 70/85/100 LL-part HY62V8200BLLSR 70/85/100 LL-part HY62V8200BLLT1-E 70/85/100 LL-part E HY62V8200BLLR1-E 70/85/100 LL-part E HY62V8200BLLST-E 70/85/100 LL-part E HY62V8200BLLSR-E 70/85/100 LL-part E HY62V8200BLLT1-I 70/85/100 LL-part I HY62V8200BLLR1-I 70/85/100 LL-part I HY62V8200BLLST-I 70/85/100 LL-part I HY62V8200BLLSR-I 70/85/100 LL-part I Note 1. Blank : Commercial, E : Extended, I : Industrial Package TSOPI(Standard) TSOPI(Reversed) Smaller TSOPI(Standard) Smaller TSOPI(Reversed) TSOPI(Standard) TSOPI(Reversed) Smaller TSOPI(Standard) Smaller TSOPI(Reversed) TSOPI(Standard) TSOPI(Reversed) Smaller TSOPI(Standard) Smaller TSOPI(Reversed)
ABSOLUTE MAXIMUM RATING (1) Symbol VIN, VOUT VCC TA Parameter Voltage on any pin relative to Vss Voltage on Vcc supply relative to Vss Operating Temperature Rating -0.2 to 3.9 -0.2 to 4.0 0 to 70 -25 to 85 -40 to 85 -55 to 150 1.0 50 260 * 5 Unit V V C C C C W mA C*sec Remark
HY62V8200B HY62V8200B-E HY62V8200B-I
TSTG Storage Temperature PD Power Dissipation IOUT Data Output Current TSOLDER Lead Soldering Temperature & Time Note 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is stress rating only and the functional operation of the device under these or any other conditions above those indicated in the operation of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect reliability.
TRUTH TABLE /CS1 H X L L L CS2 X L H H H /WE X X H H L /OE X X H L X Mode Deselected Deselected Output Disabled Read Write I/O High-Z High-Z High-Z Dout DIN Power Standby Standby Active Active Active
Note : 1. H=VIH, L=VIL, X=don't care(VIH or VIL)
Rev 06 / Apr. 2001
2
Y62V8200B Series
RECOMMENDED DC OPERATING CONDITION Symbol Vcc Vss VIH VIL Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Min. 3.0 0 2.2 -0.3(1) Typ. 3.3 0 Max. 3.6 0 Vcc+0.3 0.4 Unit V V V V
Note VIL = -1.5V for pulse width less than 30ns
DC ELCTRICAL CHARACTERISTICS Vcc= 3.0~3.6V, TA = 0C to 70C/ -25C to 85C (E)/ -40C to 85C (I), unless otherwise specified Sym. Parameter Test Condition Min. Typ. Max. ILI Input Leakage Current Vss < VIN < Vcc -1 1 ILO Output Leakage Current Vss < VOUT < Vcc, /CS1 = VIH or -1 1 CS2 = VIL or /OE = VIH or /WE = VIL Icc Operating Power Supply /CS1 = VIL, CS2 = VIH, 5 Current VIN = VIH or VIL, II/O = 0mA 35 ICC1 Average Operating Min Duty Cycle = 100%, Current /CS1 = VIL CS2 = VIH VIN = VIH or VIL 6 Cycle time = 1us, II/O = 0mA, /CS1 < 0.2V, CS2 > Vcc - 0.2V VIN < 0.2V or VIN > Vcc - 0.2V ISB TTL Standby Current /CS1 = VIH or CS2 = VIL 0.5 (TTL Input) VIN = VIH or VIL /CS1 > Vcc - 0.2V or CS2 < 0.2V, ISB1 Standby HY62V8200B 25 Current HY62V8200B-E VIN > Vcc - 0.2V or 25 (CMOS Input) HY62V8200B-I VIN < Vss + 0.2V 25 VOL Output Low Voltage IOL = 2.1mA 0.4 VOH Output High Voltage IOH = -1.0mA 2.2 Note : Typical values are at Vcc = 3.3V, TA = 25C
Unit uA uA
mA mA
mA
mA uA uA uA V V
CAPACITANCE (Temp = 25C, f= 1.0MHz) Symbol Parameter CIN Input Capacitance COUT Output Capacitance
Condition VIN = 0V VI/O = 0V
Max. 8 10
Unit pF pF
Note : These parameters are sampled and not 100% tested
Rev 06 / Apr. 2001
3
Y62V8200B Series
AC CHARACTERISTICS Vcc= 3.0V~3.6V, TA = 0C to 70C/ -25C to 85C(E)/ -40C to 85C(I), unless otherwise specified -70 -85 -10 # Symbol Parameter Min. Max. Min. Max. Min. Max. READ CYCLE 1 tRC Read Cycle Time 70 85 100 2 tAA Address Access Time 70 85 100 3 tACS Chip Select Access Time 70 85 100 4 tOE Output Enable to Output Valid 40 45 50 5 tCLZ Chip Select to Output in Low Z 10 10 10 6 tOLZ Output Enable to Output in Low Z 5 5 5 7 tCHZ Chip Deselection to Output in High Z 0 20 0 25 0 30 8 tOHZ Out Disable to Output in High Z 0 20 0 25 0 30 9 tOH Output Hold from Address Change 15 15 15 WRITE CYCLE 10 tWC Write Cycle Time 70 85 100 11 tCW Chip Selection to End of Write 60 70 80 12 tAW Address Valid to End of Write 60 70 80 13 tAS Address Set-up Time 0 0 0 14 tWP Write Pulse Width 50 60 70 15 tWR Write Recovery Time 0 0 0 16 tWHZ Write to Output in High Z 0 20 0 25 0 30 17 tDW Data to Write Time Overlap 30 35 40 18 tDH Data Hold from Write Time 0 0 0 19 tOW Output Active from End of Write 5 5 5 -
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
AC TEST CONDITIONS TA = 0C to 70C / -25C to 85C (E)/ -40C to 85C (I), unless otherwise specified Parameter Input Pulse Level Input Rise and Fall Time Input and Output Timing Reference Level Output Load tCLZ,tOLZ,tCHZ,tOHZ,tWHZ Others Value 0.4V to 2.2V 5ns 1.5V CL = 5pF + 1TTL Load CL = 100pF + 1TTL Load
AC TEST LOADS
TTL
CL(1)
Note : 1 Including jig and scope capacitance
Rev 06 / Apr. 2001
4
Y62V8200B Series
TIMING DIAGRAM READ CYCLE 1(Note1,4)
tRC ADDR tAA tACS /CS1 tOH
CS2 tCHZ(3) /OE tOLZ(3) Data Out High-Z tCLZ(3) Data Valid tOE
tOHZ(3)
READ CYCLE 2(Note 1,2,4)
tRC ADDR tAA tOH Data Out Previous Data Data Valid tOH
READ CYCLE 3(Note 1,2,4)
/CS1
CS2 tACS tCLZ(3) Data Out Data Valid tCHZ(3)
Notes: 1. A read occurs during the overlap of a low /OE, a high /WE, a low /CS1 and a high CS2. 2. /OE = VIL 3. Transition is measured + 200mV from steady state voltage. This parameter is sampled and not 100% tested. 4. /CS1 in high for the standby, low for active CS2 in low for the standby, high for active
Rev 06 / Apr. 2001
5
Y62V8200B Series
WRITE CYCLE 1(1,4,5,8) (/WE Controlled)
tWC ADDR tWR(2) tCW /CS1
CS2
tAW tWP
/WE tAS Data In High-Z tWHZ(3,7) Data Out tDW Data Valid tOW (5) (6) tDH
WRITE CYCLE 2(1,4,5,8) (/CS1, CS2 Controlled)
tWC ADDR tAS /CS1 tAW CS2 tCW tWR(2)
tWP /WE tDW Data In High-Z Data Valid tDH
Data Out
High-Z
Rev 06 / Apr. 2001
6
Y62V8200B Series
Notes(WRITE CYCLE): 1. A write occurs during the overlap of a low /WE, a low /CS1and a high CS2. A write begins at the latest transition among /CS1 going now, CS2 going high and /WE going low: A write ends at the earliest transition among /CS1 going high, CS2 low and /WE going high. tWP is measured from the beginning of write to the end of write. . 2. tCW is measured from the later of /CS1 going low or CS2 going high to the end of write . 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR1 is applied in case a write ends as /CS1, or /WE going high, and tWR2 is applied in case a write ends at CS2 going low. 5. If /OE, CS2 and /WE are in the read mode during this period, and the I/O pins are in the output low-Z state, input of opposite phase of the output must not be applied because bus contention can occur. 6. If /CS1 goes low simultaneously with /WE going low, the outputs remain in high impedance state. 7. Dout is the read data of the new address. 8. When /CS1 is low and CS2 is high, I/O pins are in the output state. The input signals in the opposite phase leading to the outputs should not be applied.
Rev 06 / Apr. 2001
7
Y62V8200B Series
DATA RETENTION ELECTRIC CHARACTERISTIC TA = 0C to 70C / -25C to 85C (E)/ -40C to 85C (I) Symbol Parameter Test Condition VDR Vcc for Data Retention /CS1>Vcc - 0.2V or CS2<0.2V, VIN>Vcc - 0.2V or VIN>Vss + 0.2V ICCDR Data HY62V8200B Vcc=3.0V, Retention HY62V8200B-E /CS1>Vcc - 0.2V or CS2<0.2V, Current HY62V8200B-I VIN>Vcc - 0.2V or VIN>Vss + 0.2V tCDR Chip Deselect to Data See Data Retention Timing Retention Time Diagram tR Operating Recovery Time Notes: 1. Typical values are under the condition of TA = 25C.
Min. 2.0 0 5
Typ. -
Max. 25 25 25 -
Unit V uA uA uA ns ms
DATA RETENTION TIMING DIAGRAM 1
VCC 3.0V tCDR
DATA RETENTION MODE tR
2.2V VDR CS1>VCC-0.2V CS1 VSS
DATA RETENTION TIMING DIAGRAM 2
VCC 3.0V CS2 VDR tCDR
DATA RETENTION MODE tR
0.4V VSS CS2<0.2V
Rev 06 / Apr. 2001
8
Y62V8200B Series
PACKAGE INFORMATION 32pin 8x20mm Thin Small Outline Package Standard(T1)
#1
#32 UNIT : INCH(mm)
0.319(8.103) 0.311(7.900)
#16 0.728(18.491) 0.720(18.288) 0.792(20.117) 0.784(19.914)
#17
0.041(1.05) 0.037(0.95) 0.006(0.15) 0.002(0.05) 0.025(0.64) 0.021(0.54) 0.008(0.21) 0.004(0.10) 0.020(0.50) BSC 0.011(0.27) 0.007(0.17)
32pin 8x20mm Thin Small Outline Package Reversed(R1)
#16
#17 UNIT : INCH(mm)
0.319(8.103) 0.311(7.900)
#1 0.728(18.491) 0.720(18.288) 0.792(20.117) 0.784(19.914)
#32
0.041(1.05) 0.037(0.95) 0.006(0.15) 0.002(0.05) 0.025(0.64) 0.021(0.54) 0.008(0.21) 0.004(0.1) 0.020(0.50) BSC 0.011(0.27) 0.007(0.17)
Rev 06 / Apr. 2001
9
Y62V8200B Series
32pin 8x13.4mm Smaller Thin Small Outline Package Standard(ST)
#1
#32 0.319(8.1) 0.311(7.9) UNIT : INCH(mm)
#16 0.468(11.9) 0.460(11.7) 0.536(13.6) 0.520(13.2)
#17
0.041(1.05) 0.037(0.95) 0.008(0.20) 0.002(0.05) 0.024(0.6) 0.016(0.4) 0.008(0.2) 0.004(0.1) 0.020(0.50) 0.011(0.27) 0.007(0.17)
32pin 8x13.4mm Smaller Thin Small Outline Package Reversed(SR)
#16
#17 0.319(8.1) 0.311(7.9) UNIT : INCH(mm)
#1 0.468(11.9) 0.460(11.7) 0.536(13.6) 0.520(13.2)
#32
0.041(1.05) 0.037(0.95) 0.008(0.20) 0.002(0.05) 0.024(0.6) 0.016(0.4) 0.008(0.2) 0.004(0.1) 0.020(0.50) 0.011(0.27) 0.007(0.17)
Rev 06 / Apr. 2001
10
Y62V8200B Series
MARKING INFORMATION
Package
h y Y y n 6 w i 2 w
Marking Example
x V p 8 2 0 c 0 c B T 1 s s t K O R E A
TSOP-I
H y
H
Y c y
6 S w
2 T w
V p
8 s
2 s
0 t K
0
B
sTSOP
c y
O
R
Index
* hynix * KOREA / KOR * HY62V8200B * yy * ww *p * cc : hynix Logo : Origin Country : Part Name : Year ( ex : 00 = year 2000, 01 = year 2001 ) : Work Week ( ex : 12 = ww12 ) : Process Code : Power Consumption -L : Low Power - LL : Low Low Power : Package Type - T1 : TSOP-I - ST : sTSOP : Speed - 70 : 70ns - 85 : 85ns : Temperature - Blank : Commercial ( 0 ~ 70 C ) -E : Extended ( -25 ~ 85 C ) -I : Industrial ( -40 ~ 85 C ) : Fixed Item : Non-fixed Item (Except hynix)
* T1 / ST
* ss
*t
Note - Capital Letter - Small Letter
Rev 06 / Apr. 2001
11

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